BIOS Boot Sequence - A Closer Look

1. Internal power supply turns on, initializes and then takes few moments to generate reliable power for rest of the system. If power received is not within expectd parameters (by chipset and subsequently processor), then the chipset will generate a reset signal to the processor in the same fashion as you were to touch the reset button. This will continue until motherboard receives "Power Good" signal from power supply
2. Since processor has no idea on what to do next as there is nothing to execute in memory, it has been designed to look at the same place in the system, the BIOS ROM, for the small bit of startup code to begin the boot process (CS = 0xFFFF and EIP = zero => 0xFFFF0). Since there are 16 bytes (total is FFFFF), this location contains just a "jump" instruction telling the processor where to go to find the real BIOS startup program (see the diagram).
3. BIOS then performs POST (Power-On Self Test). If there are any fatal errors, the boot process stops. If the POST is successful, the BIOS calls INT 19 (Interrupt 19) and then proceeds to look for devices attached to the motherboard
4. BIOS enables the video: The BIOS code begins searching by looking for a video card, and video card's built in BIOS program (normally at 0xC000 in memory) and if found, it runs it.
5. Once video is enabled, the BIOS begins searching for other devices that may have their own ROM and whether ROM has its own BIOS code. Normally, the floppy driver is located at 0000:7c00 and the IDE/ATA HDD BIOS will be found at C8000h. If any of these is found, their codes are executed. If during this INT 19 process, any other device BIOS's are found, they are executed as well
6. BIOS displays its startup screen, which provides some key information about the BIOS as well as other system information
7. BIOS then performs some kind of inventory of the hardware installed in the system and then communicates or interrogates it to ensure that the hardware is functioning (at this stage, BIOS will populate BIOS table, can be ACPI table, if the system is ACPI compliant. This table can be used by several purposes including power management, by the OS applications)
8. During the final phase of POST and BIOS boot process, the BIOS will display a summary screen with your systems' configuration.
9. NOW, BIOS finishes what it needs to do, it begins searching for a drive to boot an OS. If its searching a hard disk, it looks for a MBR at cylinder 0, head 0 and sector 1, the first sector on the disk. If its searching for Floppy disk, it looks at the same address on the floppy disk for a volume boot sector
10. Once the boot sector is found, BIOS starts the process of booting OS by using the info in boot sector. If its floppy, the boot sector is also read into memory at 0000:7C00 and then MBR program itself jumps to memory location 0000:7c00 (NOTE: Each OS has its own boot sector format. The next step involves the small program in the boot sector locating the first part of OS's kernel loader proram or in some cases the kernel itself or perhaps a boot manager program, and read then that into memory. In windows, this kernel loader referred to as NTLDR.
11. If no boot device of any type can be found, the system will display an error message and stop.

NOTE: This entire process is called as "cold boot" (since the machine was off, or cold, when it started). A "warm boot" also known as "soft boot" is the same thing except it occurs when the machine is rebooted using Ctrl+Alt+Del keys. In this case, POST is skipped and boot process continues at roughly step 8 above. As a side note, INT19 is also called when the CTRL+ALT+DEL keys are used.

MBR and its necessary

1. When you turn on your PC, the processor does not really have anything to execute or even know where to look for it. To ensure that the PC will always boot regardless of BIOS, bot chip and BIOS manufractures developed their code so that the processor, once turned on, always starts executing at the same place, FFFF0h. This magical address is called "reset vector"

(NOTE: Similarly, every hard disk must have a consistent "starting point" where the key information is stored about the disk, such as number of partitions and their types. There also must be someplace where the BIOS can load the initial boot program that starts the process of loading the OS and this place is called Master Boot Record - MBR, also referred to as Master Boot Sector - MBS or even just Boot Sector - BS)

2. MBR is always located at cylinder 0, head 0 and sector 1, the first sector on the disk (512 bytes). When a computer starts and the BIOS boots the machine, it will always look at this first sector for instructions and information on how to proceed with the boot process and load the OS.

3. MBR contains following structures

• Master Partition Table (MPT): Small bit of code that is referred to as a table contains a complete description of the partitions that are contained on the HDD. (Alas!!.. when the developers designed the size of this MPT, they left juz enuf room for description of 4 partitions, and hence the four partition [four physical partitions] limit. Any additional partions must be logical partitions that are linked to (or are part of) one of the primary partitions.) One of these partitions is marked as active, indicating that it is the one that the computer should used to continue the boot process
• Master Boot Code (MBC): MBC is a small bit of computer code that the BIOS loads and executes to start the boot process. This code, when fully executed transfers control to boot program stored in boot (active) partition to load the operating system (NOTE: MBC is the first program executed when you turn on your PC, and is often the target of a virus)

4. BIOS however, does not care about any of this: it simply loads the contents of the MBR into memory location 0x7c00 and jumps to that location to start executing whatever code is in the MBR.

Traditionally, Microsoft MBR code takes a look at the partition table, finds the (only) partition marked as active, loads the boot sector for that partition, and runs that code. This boot sector is the first sector of a partition, as opposed to the first sector for the whole disk. If something is wrong with the partition table, you would get messages like "Invalid Partition Table" or "Missing Operating System". This message does not come from BIOS but rather from MBR code loaded from disk.

Linux boot loaders LiLo and GRUB (GRand Uniform Boot) loader can handle a wide variety of OSs, file systems and boot configurations. Their MBR code does not necessarily follow the "boot the active partition" approach described above. But functionally the process goes like this:

1. MBR itself contains the first stage of boot loader. GRUB calls this stage 1.

2. Due to its tiny size, the code in MBR does just enuf to load another sector from disk that contains additional bootstrap code. This sector might be the boot sector for a partition, but could also be a sector that was hard-coded into the MBR code when the MBR was installed.

3. MBR code plus code loaded in step 2, then read a file containing the second stage of the boot loader. In GRUB, this is GRUB Stage 2, and in Windows Server, this is C:\NTLDR. If step 2 fails in windows, you 'd get message like "NTLDR is missing". This stage 2 code then reads a boot configuration file (eg., grub.conf in GRUB, boot.ini in windows). It then presents boot choices to the user or simply goes ahead in a single-boot system.

4. At this point, the boot loader code needs to fire up a kernel. It must know enuf about file systems to read the kernel from the boot partition. In Linux, this means reading a file like "vmlinuz-2.6.22-14-server" containing the kernel, loading the file into memory and jumping to the kernel bootstrap code. In Windows Server 2003, some of the kernel start-up code is separte from the kernel image itself and is actually embedded into NTLDR. After performing several initializations, NTLDR loads the kernel image from file C:\Windows\System32\ntoskrnl.exe, just as GRUB does, jumps to kernel entry point.

What is IPMI basic working "algorithm"?

Block Diagram of IPMI

What is IPMI?

1. What is "Platform Management"?

• Monitoring and control functions that are built in to the platform hardware and primarily used for the purpose of monitoring the health of the system hardware (includes monitoring elements such as System Temperatures, voltages, fans, power supplies, bus errors, system physical security etc)
• Inventory, monitoring, logging and recovery functions

2. What is "Intelligent Platform Management (IPM)"?

• The above functions available independent of the main processors, BIOS and OS.
• Also available when the system is in powered down state.

3. What is "Intelligent Platform Management Interface (IPMI)"?

• Hardware level interface specification providing "above" functions, that can be exposed thro' standard management software interfaces such as DMI, WMI, CIM, SNMP etc (see fig below)

More on RPM Files and Spec Files

http://linuxshellaccount.blogspot.com/2008/03/beginning-your-spec-file-for-building.html

How the EXE is loaded into main memory for execution - The system Program Loader

Once BIOS hands control over to the OS, you may then request execution of a program.

NOTE: The program can be either .COM or .EXE. A .COM program is useful as a small utility program or as a resident program (one that is installed in memory and is available while other programs run). In real mode, an .EXE program consists of separate code, data and stack segments and is the method used for more serious programs.

When you double click on an .EXE program (when you request the system to load an .EXE program from disk into memory for execution), the System Program Loader performs following steps

1. Accesses the .EXE program from disk
2. Constructs a 256-byte (100H) Program Segment Prefix (PSP) on a paragraph boundary in available internal memory (NOTE: PSP is a data structure used in DOS systems to store the state of a program)
3. Stores the program in memory immediately following PSP
4. Loads the address of PSP in DS and ES registers
5. Loads the address of code segment in CS register and sets the IP register to the offset of the first instruction (usually zero) in the code segment
6. Loads the address of the stack in SS register and sets the SP register to the size of the stack
7. Transfers control to the program for execution, beginning usually with the first instruction in the code segment
   

The BIOS Boot Process

1. Turning on Computers' power causes the processor to enter a reset state, clears all memory locations to zero, perform a parity check of memory and set the CS register to segment address FFFFh and IP register to zero.

2. Hence the first instruction to execute, therefore is at address formed by CS:IP pair, which is FFFF0H, the entry point to BIOS in ROM

3. BIOS routine at FFFF0H checks the various ports to identify and initialize devices taht are attached to the computer and provides services that are used for reading to and for writing from the devices.

4. BIOS then establishes two data areas -

• IVT (Interrupt Vector Table): Begins in low memory at location 0 and contains 256 4-bytes address in the form of segment:offset (Both BIOS and OS uses these IVT for interrupts that occur)
• BIOS data Areas: Beginning at location 400H, largely concerned with the status of attached devices

5. BIOS next determines whether a disk containing the system files is present and, if so, it accesses the bootstrap loader from the disk

6. This BSP (Boot strap program) loads system files from the disk into memory and transfers control to them (System files contains device drivers and other hardware-specific code which initializes internal system tables and the systems' portion of IVT)

NOTE: When a user program requests an IO services of OS, it transfers request to BIOS, which in turn accesses requested device. Sometimes, program makes requests directly to BIOS, such as keyboard and screen services. At other times, a program can bypass both OS and BIOS to access a device directly

CPU Registers

CPU registers are classified into five categories as follows

1. Segment registers
2. Pointer registers
3. General Purpose registers
4. Index registers
5. Flags register

1. Segment registers

• Segments (20-bit wide) are special areas defined in a program for containing the code, the data and stack.
• segment begins on a paragraph boundary; that is at a location evenly divisible by 16
• segment registers are 16-bit size and contains starting address of the segment (Reason: since segments are starting on a paragraph boundary, the designers decided that it would be unnecessary to store the zero digit in the segment register)
• Offset is 16 bits wide (and is specified in Pointer registers described later)
• Further classified into Code, data, stack and extra - corresponds to CS, DS, SS, ES, FS and GS registers

2. Pointer registers

• Pointer registers are 32-bit EIP, ESP and EBP; the rightmost are IP, SP and BP respectively (16-bit wider as mentioned above)
• IP register is associated with CS register (as CS:IP => Segment:Offset)

Example - Segment address in CS 39B40h

Offset address in IP +0514h

------------

Address of next instruction 3A054h

------------

• SP register is associated with SS register (as SS:SP => Segment:Offset)

Example - Segment address in SS 39B40h

Offset address in SP +0514h

------------

Address in stack 3A054h

------------

• BP facilitates referencing parameters, which are data and addresses that a program passes via the stack. Processor combines the address in SS with the offset in BP. BP can also be combined with DI and with SI as a base register for special addressing.

3. General Purpose registers

• 32-bit general purpose registers
• AX - primary accumulator - used for operations involving input/output and most arithmetic - more efficient compared to other registers
• BX - base register - only register used as an index to extend addressing - can also be combined with DI or SI as a base register for special addressing
• CX - count register - may contain a value to control the number of times a loop is repeated or a value to shift bits left or right
• DX - data regsiter - works with AX sometimes, to compute operations that involve large values

4. Index registers

• SI (soure index) - may be required for some string (character) handling operations - in this context, SI is associated with DS register (as DS:SI)
• DI (destination index) - is required for some string operations - in this context, DI is associated with ES register

5. Flags register

• 32 bit wder
• OF (overflow), IF (interrupt), TF (trap), SF (sign), ZF (zero), AF (auxiliary carry), PF (parity) and CF (carry)

Execution unit and Bus Interface Unit

Processor is partitioned into two logical units

1. Execution unit (EU) - to execute instructions

2. Bus Interface Unit (BIU) - to deliver instructions and data to EU

Execution unit:

• Maintains CPU status and control flags
• manipulates general registers and instruction operands. (Registers and data paths are 16 bits wider)
• has no connection to "outside world". 
• obtains instructions from Instruction Q maintained by BIU.
• when an instruction requires access to memory or to a peripheral device, EU requests the BIU to obtain or store the data

Bus Interface unit:

• performs all bus operations for EU
• data transferred between CPU and momory/IO devices upon demand from EU
• during periods, when EU is busy executing instructions, the BIU "looks ahead" and fetches more instructions from memory.
• these instructions are stores in an internal RAM array called "Instruction Stream Q" - from which EU takes instructions to execute

Processor history