More on RPM Files and Spec Files

http://linuxshellaccount.blogspot.com/2008/03/beginning-your-spec-file-for-building.html

How the EXE is loaded into main memory for execution - The system Program Loader

Once BIOS hands control over to the OS, you may then request execution of a program.

NOTE: The program can be either .COM or .EXE. A .COM program is useful as a small utility program or as a resident program (one that is installed in memory and is available while other programs run). In real mode, an .EXE program consists of separate code, data and stack segments and is the method used for more serious programs.

When you double click on an .EXE program (when you request the system to load an .EXE program from disk into memory for execution), the System Program Loader performs following steps

1. Accesses the .EXE program from disk
2. Constructs a 256-byte (100H) Program Segment Prefix (PSP) on a paragraph boundary in available internal memory (NOTE: PSP is a data structure used in DOS systems to store the state of a program)
3. Stores the program in memory immediately following PSP
4. Loads the address of PSP in DS and ES registers
5. Loads the address of code segment in CS register and sets the IP register to the offset of the first instruction (usually zero) in the code segment
6. Loads the address of the stack in SS register and sets the SP register to the size of the stack
7. Transfers control to the program for execution, beginning usually with the first instruction in the code segment
   

The BIOS Boot Process

1. Turning on Computers' power causes the processor to enter a reset state, clears all memory locations to zero, perform a parity check of memory and set the CS register to segment address FFFFh and IP register to zero.

2. Hence the first instruction to execute, therefore is at address formed by CS:IP pair, which is FFFF0H, the entry point to BIOS in ROM

3. BIOS routine at FFFF0H checks the various ports to identify and initialize devices taht are attached to the computer and provides services that are used for reading to and for writing from the devices.

4. BIOS then establishes two data areas -

• IVT (Interrupt Vector Table): Begins in low memory at location 0 and contains 256 4-bytes address in the form of segment:offset (Both BIOS and OS uses these IVT for interrupts that occur)
• BIOS data Areas: Beginning at location 400H, largely concerned with the status of attached devices

5. BIOS next determines whether a disk containing the system files is present and, if so, it accesses the bootstrap loader from the disk

6. This BSP (Boot strap program) loads system files from the disk into memory and transfers control to them (System files contains device drivers and other hardware-specific code which initializes internal system tables and the systems' portion of IVT)

NOTE: When a user program requests an IO services of OS, it transfers request to BIOS, which in turn accesses requested device. Sometimes, program makes requests directly to BIOS, such as keyboard and screen services. At other times, a program can bypass both OS and BIOS to access a device directly

CPU Registers

CPU registers are classified into five categories as follows

1. Segment registers
2. Pointer registers
3. General Purpose registers
4. Index registers
5. Flags register

1. Segment registers

• Segments (20-bit wide) are special areas defined in a program for containing the code, the data and stack.
• segment begins on a paragraph boundary; that is at a location evenly divisible by 16
• segment registers are 16-bit size and contains starting address of the segment (Reason: since segments are starting on a paragraph boundary, the designers decided that it would be unnecessary to store the zero digit in the segment register)
• Offset is 16 bits wide (and is specified in Pointer registers described later)
• Further classified into Code, data, stack and extra - corresponds to CS, DS, SS, ES, FS and GS registers

2. Pointer registers

• Pointer registers are 32-bit EIP, ESP and EBP; the rightmost are IP, SP and BP respectively (16-bit wider as mentioned above)
• IP register is associated with CS register (as CS:IP => Segment:Offset)

Example - Segment address in CS 39B40h

Offset address in IP +0514h

------------

Address of next instruction 3A054h

------------

• SP register is associated with SS register (as SS:SP => Segment:Offset)

Example - Segment address in SS 39B40h

Offset address in SP +0514h

------------

Address in stack 3A054h

------------

• BP facilitates referencing parameters, which are data and addresses that a program passes via the stack. Processor combines the address in SS with the offset in BP. BP can also be combined with DI and with SI as a base register for special addressing.

3. General Purpose registers

• 32-bit general purpose registers
• AX - primary accumulator - used for operations involving input/output and most arithmetic - more efficient compared to other registers
• BX - base register - only register used as an index to extend addressing - can also be combined with DI or SI as a base register for special addressing
• CX - count register - may contain a value to control the number of times a loop is repeated or a value to shift bits left or right
• DX - data regsiter - works with AX sometimes, to compute operations that involve large values

4. Index registers

• SI (soure index) - may be required for some string (character) handling operations - in this context, SI is associated with DS register (as DS:SI)
• DI (destination index) - is required for some string operations - in this context, DI is associated with ES register

5. Flags register

• 32 bit wder
• OF (overflow), IF (interrupt), TF (trap), SF (sign), ZF (zero), AF (auxiliary carry), PF (parity) and CF (carry)

Execution unit and Bus Interface Unit

Processor is partitioned into two logical units

1. Execution unit (EU) - to execute instructions

2. Bus Interface Unit (BIU) - to deliver instructions and data to EU

Execution unit:

• Maintains CPU status and control flags
• manipulates general registers and instruction operands. (Registers and data paths are 16 bits wider)
• has no connection to "outside world". 
• obtains instructions from Instruction Q maintained by BIU.
• when an instruction requires access to memory or to a peripheral device, EU requests the BIU to obtain or store the data

Bus Interface unit:

• performs all bus operations for EU
• data transferred between CPU and momory/IO devices upon demand from EU
• during periods, when EU is busy executing instructions, the BIU "looks ahead" and fetches more instructions from memory.
• these instructions are stores in an internal RAM array called "Instruction Stream Q" - from which EU takes instructions to execute

Processor history